1. Field of the Invention
The present invention relates to a reference voltage generation circuit and a reference voltage distributing method, and relates to a reference voltage generation circuit and a reference voltage distributing method which are favorable for use in the case of generating reference voltages to be applied to constant current sources included in non-saturation type logic circuits (e.g., CML, Current Mode Logic, or ECL, Emitter Coupled Logic) which are provided in an LSI (Large Scale Integrated Circuit) or the like including a number of circuits (e.g., flip-flops), and supply clocks to the respective circuits (e.g., flip-flops).
2. Description of Related Art
In an LSI including a number of flip-flops, it is necessary to prevent a malfunction of each of the flip-flops due to a deviation of the timing (clock skew) of a clock which is distributed and supplied to each of the flip-flops.
In FIG. 4, a clock is supplied to each flip-flop (not illustrated in FIG. 4), via a clock wiring 2, which is a tree structural wiring, from a clock supply source, which is installed outside an LSI 1. If clock delays become equal because of the structure of the clock wiring 2, then the clock skew becomes zero. In a high-speed serial transmission such as SerDes (Serialization/Deserialization), a high frequency clock is required. However, an edge shift of the high frequency clock (i.e., clock jitter) significantly influences the error rate of transmission.
Therefore, in recent years, a CML circuit or an ECL circuit which has a resistance against a power source is used as a clock driver. In such a clock driver, the CML circuit or an ECL circuit is configured by a MOS transistor capable of high-speed operation with a small amplitude.
The CML circuit and the ECL circuit is an analog circuit which requires a reference voltage. When a clock is distributed and supplied to the flip-flop by using such an analog circuit requiring the reference voltage as the clock driver in the region across a wide range of the LSI 1, if the reference voltage is distributed in a voltage mode, there arises a problem of being easily influenced by a crosstalk noise from a periphery of the LSI 1 and a noise caused by the CML or ECL circuit itself Another problem arises of a malfunction to a variation in the operation process of the LSI 1 or a gradient of the reference voltage of the LSI 1.
Further, when a shield wiring is installed to prevent the influence of the crosstalk noise, there arises another problem that an occupation area of a hardware configuration of the LSI 1 becomes larger and/or complex.
It is possible to install a feedback circuit to generate the reference voltage, the feedback circuit being configured by a replica circuit and an operational amplifier. In this case, since variation in the operation process of the LSI 1 can be cancelled and the distribution range of the reference voltage can be made narrow, the influence of the crosstalk noise will decrease. However, since the feedback circuit is needed to be installed corresponding to each of the clock drivers, the occupation area for the feedback circuit will be increased.
Further, since a plurality of loops of the feedback circuits exist in the LSI 1 and a state in which the operations differ among the respective feedback circuits easily occurs, therefore, this configuration easily causes the clock skew and the clock jitter.
As the related art, for example, there is a Patent Document 1.
In a differential output driver described in Patent Document 1, a constant current generator is provided at one spot inside an integrated circuit chip. The constant current generator distributes a reference current to each of the differential output driver in the integrated circuit chip, and a differential signal output unit is controlled by the reference current. The reference current which is distributed by the constant current generator is inputted into a first current mirror circuit The output current of the first current mirror circuit is inputted into a second current mirror circuit. The output current of the second current mirror circuit is inputted into the differential signal output unit.
[Patent Document 1] Japanese Patent Laid-Open No. 10-065515